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features ? 1300 nm single mode transceiver for links up to 15 km ? compliant with atm forum 155.52 mb/s physical layer specification af-phy-0046.000 ? compliant with specifica- tions proposed to ansi t1e1.2 committee for inclusion in t1.646-1995 broadband isdn and t1e1.2/96-002 sonet network to customer installation interface standards ? compliant with ansi t1.105.06 sonet physical layer specifications standard ? multisourced 2 x 9 pin-out package style ? integral duplex sc connector receptacle compliant with tia/eia and iec standards ? single +5 v power supply operation and pecl logic interfaces ? incorporates hewlett- packards eyesafe laser subassembly ? integral digital pll provides regenerated differential clock output ? integral decision circuit provides retimed differential data output ? laser bias monitor, refer- ence clock, transmitter disable and laser power monitor functions ? two temperature ranges: 0 c to +70 c - HFCT-5202b/d C40 c to +85 c C hfct- 5202a/c ? wave solder and aqueous wash process compatible ? manufactured in an iso 9001 certified facility applications ? atm 155 mb/s links ? sonet oc-3/sdh stm-1 interconnections 155 mb/s single mode fiber transceiver with integrated clock and data recovery for atm, sonet oc-3/sdh stm-1 technical data HFCT-5202 description general the HFCT-5202 is a 1300 nm laser-based duplex sc receptacle 2 x 9 transceiver with integral clock and data recovery circuits. it provides a cost-effective solution to medium haul 155 mb/s data link requirements. this compact transceiver requires a single +5 v source and contains the following data, clock and monitoring features as depicted in figure 1: differential data input, differential retimed data output, recovered clock output, signal detect, laser bias monitor, transmitter disable, and an option
2 figure 1. block diagram. figure 2. relative timing relationship between output retimed data and recovered clock signals. to generate a local timing signal from an external, low-frequency reference clock. the external timing signal acts as the reference clock when incoming optical signals become undetectable. transmitter section the transmitter section of the HFCT-5202 is similar to other hewlett-packard 1300 nm single mode transceivers in use at the 155 mb/s data rate. it consists of a 1300 nm ingaasp laser in an eye-safe optical subassembly (osa) which mates to the fiber cable. the laser osa is driven by a custom, silicon bipolar ic which converts differential input pecl logic signal into an analog laser drive current. receiver section the receiver section of the transceiver provides a full set of features including an integral clock and data recovery (cdr) circuit together with an optional, selectable receiver local clock source. the receiver utilizes an ingaas pin photodiode mounted together with a transimpedance preamplifier ic in an osa. this osa is connected to a custom, silicon bipolar circuit providing post-amplification and quantiza- tion, cdr function, and optical signal detection. cdr function in normal operation, the cdr data loop is able to acquire and maintain bit lock without the use of the optional, external refer- ence clock. this loop consists of a patented phase/frequency detector with false-lock protec- tion. the recovered clock is used to retime the quantizer data output, which completes the full cdr function. the relative timing relationship between the output retimed data and the recovered clock signals is shown graphically in figure 2. signal detect electrical subassembly clock & data recovery and post amplifier ic laser driver ic top view pin photodiode duplex sc receptacle laser pre- amplifier ic retimed data 2 data 2 optical sub- assemblies recovered clock 2 reference clock lock-to-reference laser bias monitor power monitor transmit disable baud interval rd rd clk clk v oh v ol v oh v ol v oh v ol v oh v ol clock period
3 for input optical power greater than the specified receiver sensitivity of -28 dbm, the bit- error-ratio will be better than 1x10 -10 . as the input power is decreased by several db, the bit- error-ratio degrades. within 1 db below the 1 x 10 -2 ber input optical power level, the cdr will begin to lose lock and the clock frequency will drift from 155.52 mhz. once the cdr loses lock, the clock frequency will sweep through the entire vco range, about 140 to 200 mhz. the rate of the sweep is inversely propor- tional to the input optical power and will reach its maximum at a point of 2 db below the lock point. since data is retimed to the clock, a loss of lock will produce an output data stream consisting of randomly switching data bits, i.e., noise. receiver signal detect as the input optical power is decreased, signal detect will switch from high to low (de- assert point) at a point between 3 db below minimum guaranteed sensitivity and the no light input level. as the input optical power is increased from very low levels, signal detect will switch back from low to high (assert point). the assert level will be at least 0.5 db higher than the de-assert level. this single-ended low- power pecl output is designed to drive a standard pecl input using a 10 k w load instead of the normal 50 w pecl load. reference clock in applications where the receiver recovered clock frequency is not allowed to drift upon loss of input optical signal, the HFCT-5202 has the ability to generate a local clock output by multiplying an optional, external 19.44 mhz reference clock up to the oc-3/stm1 155.52 mhz rate. this feature is possible because the clock recovery system consists of two loops: a data loop which locks onto the incoming optical data stream, and a second reference loop which locks onto the optional external reference clock. this optional feature is initiated by applying a lock-to-reference logic signal to pin 2 (lck ref-) which switches the loop to the external reference clock and disables the received data outputs. pin 2 (lck ref-) can be driven from the signal detect pin 15 (sd) output or from other logic further upstream in the atm interface which may be monitoring the quality of the received data stream. transceiver specified for wide temperature range operation the HFCT-5202 is specified for operation over normal commer- cial temperature range of 0 to +70 c (HFCT-5202b/d) or the extended temperature range of C40 c to +85 c (HFCT-5202a/c). other members of hp 155 mb/s product family ? hfct-5205, 1300 nm laser- based 1 x 9 sc receptacle transceiver for 15 km links with smf cables (without cdr) ? hfbr-5208 1300 nm led based 1 x 9 sc receptacle transceiver for 500 m links with mmf cables (drop in replacement for hfct-5205) ? xmt5370-155 1300 nm laser- based transmitter in pigtailed package for 15 km links with smf cables ? xmt5170-155 1300 nm laser- based transmitter in pigtailed package for 40 km links with smf cables ? rcv1201d-155 receiver in pigtailed package for 15 km and 40 km links with smf cables ? rgr1551 receiver with integral clock and data recovery in pigtailed packages for 15 km applications information typical ber performance of receiver versus input optical power level the HFCT-5202 transceiver can be operated at bit-error-rate conditions other than the required ber = 1 x 10 -10 of the atm forum 155.52 mb/s physical layer standard. the typical tradeoff of ber versus relative input optical power is shown in figure 3. the relative input optical power in db is referenced to the input optical power parameter value in the receiver optical characteristics table. for figure 3. relative input optical powerCdbm avg. bit error ratio -5 3 10 -2 relative input optical power ?dbm avg. -3 1 -2 0 10 -4 10 -6 10 -8 10 -10 10 -11 10 -12 10 -7 10 -5 10 -3 -4 -1 2 10 -9 10 -13 10 -14 10 -15 linear extrapolation of 10 -4 through 10 -7 data points actual data points
4 better ber condition than 1x10 -10 , more input signal is needed (+db). recommended circuit schematic in order to insure proper functionality of the HFCT-5202 a recommended circuit is provided in figure 4. when designing the circuit interface, there are a few fundamental guidelines to follow. for example, in the recom- mended circuit schematic figure the differential data lines should be treated as 50 ohm microstrip or stripline transmission lines. this will help to minimize the parasitic inductance and capaci- tance effects. proper termination of the differential data and clock signals will prevent reflections and ringing which would compromise the signal fidelity and generate unwanted electrical noise. locate termination at the received signal end of the transmission line. the length of these lines should be kept short and of equal length to prevent pulse-width distortion and data- to-clock timing skew from occurring. for the high speed signal lines, differential signals should be used, not single-ended signals, and these differential signals need to be loaded sym- metrically to prevent unbalanced currents from flowing which will cause distortion in the signal. maintain a solid, low inductance ground plane for returning signal currents to the power supply. multilayer plane printed circuit board is best for distribution of v cc , returning ground currents, forming transmission lines and shielding. also, it is important to suppress noise from influencing the fiber-optic transceiver performance, especially the figure 4. recommended circuit schematic. receiver and the clock recovery circuits. proper power supply filtering of v cc for this transceiver is accomplished by using the recommended, separate filter circuits shown in figure 4, the recommended circuit schematic diagram, for the transmitter and receiver sections. these filter circuits suppress v cc noise of 50 mv peak-to-peak or less over a broad frequency range. this prevents receiver sensitivity degradation as well as false-lock or loss-of-lock in the clock recovery circuitry due to v cc noise. it is recommended that surface-mount components be used. use tantalum capacitors for the 10 m f capacitors and monolithic, ceramic bypass capacitors for the 0.1 m f locate filter at v cc pins r7 r6 r8 v cc c3 c4 l1 l2 c1 c2 r15 r1 r4 c5 r3 r2 v cc terminate at fiber-optic transceiver inputs terminate at the device inputs c8 r12 r10 r9 r14 c7 r11 r13 v cc clk clk r5 c6 1 ref clk 2 lck ref 3 clk 4 clk 5* l mon (-) 6* l mon (+) 7* t xdis 8* nc 9* p mon 18 17 rd 16 rd 15 sd 14 13 12 td 11 td 10 rx v ee rx v cc tx v cc tx v ee terminate at clock inputs ref clk HFCT-5202 top view no internal connection no internal connection notes: the split-load terminations for pecl signals need to be located at the input of devices receiving those pecl signals. r1 = r4 = r6 = r8 = r10 = r12 = r14 = 130 w . r2 = r3 = r5 = r7 = r9 = r11 = r13 = 82 w . c1 = c2 = c3 = c5 = c6 = c7 = 0.1 ?. c4 = c8 = 10 ?. l1 = l2 = 1 ? coil. r15 = 10 k w . for the single mode HFCT-5202 transceiver, pins 5 - 9 are used for laser diode bias and optical power monitoring as well as to provide a transmitter disable function. *for the multimode hfbr-5207 transceiver, pins 5 - 9 are not used. optional rd rd sd v cc td td rx tx
5 capacitors. also, it is recom- mended that a surface-mount coil inductor of 1 m h be used. ferrite beads can be used to replace the coil inductors when using quieter v cc supplies, but a coil inductor is recommended over a ferrite bead. coils with a low, series dc resistance (<0.7 ohms) and high, self-resonating frequency are recommended. all power supply components need to be placed physically next to the v cc pins of the receiver and transmitter. use a good, uniform ground plane with a minimum number of holes to provide a low-inductance ground current return for the power supply currents. in addition to these recommenda- tions, hewlett-packards applica- tion engineering staff is available for consulting on best layout practices with various vendors mux/demux, clock generator and clock recovery circuits. hp has participated in several reference design studies and is prepared to share the findings of these studies with interested customers. contact your local hp sales representative to arrange for this service. evaluation circuit boards evaluation circuit boards implementing this recommended circuit design are available from hewlett-packards application engineering staff. contact your local hp sales representative to arrange for access to one if needed. operation in -5.2 v designs for applications that require -5.2 v dc power supply level for true ecl logic circuits, the HFCT-5202 transceiver can be operated with a v cc = 0 v dc and a v ee = -5.2 v dc. this transceiver is not specified with an operating, negative power supply voltage. the potential compromises that can occur with use of -5.2 v dc power are that the absolute voltage states for v oh and v ol will be changed slightly due to the 0.2 v differ- ence in supply levels. also, noise immunity may be compromised for the HFCT-5202 transceiver because the ground plane is now the v cc supply point. the suggested power supply filter circuit shown in figure 4 recommended circuit schematic should be located in the v ee paths at the transceiver supply pins. direct coupling of the differential data and clock signals can be done between the hfct- 5202 transceiver and the standard ecl circuits. for guaranteed -5.2 v dc operation, contact your local hewlett- packard field sales engineer for assistance. recommended solder and wash process the HFCT-5202 is compatible with industry standard wave or hand solder processes. HFCT-5202 process plug the HFCT-5202 transceiver is supplied with a process plug for protection of the optical ports with the duplex sc connector receptacle. this process plug prevents contamination during wave solder and aqueous rinse as well as during handling, shipping, or storage. it is made of high- temperature, molded, sealing material that will withstand +80 c and a rinse pressure of 50 lb/in 2 . recommended solder fluxes and cleaning/degreasing chemicals solder fluxes used with the HFCT-5202 fiber-optic transceiver should be water- soluble, organic solder fluxes. some recommended solder fluxes are lonco 3355-11 from london chemical west, inc. of burbank, ca, and 100 flux from alpha- metals of jersey city, n.j. recommended cleaning and degreasing chemicals for the HFCT-5202 are alcohols (methyl, isopropyl, isobutyl), aliphatics (hexane, heptane), and other chemicals, such as soap solution or naphtha. do not use partially halogenated hydrocarbons for cleaning/degreasing. examples of chemicals to avoid are 1.1.1. trichloroethane, ketones (such as mek), acetone, chloroform, ethyl acetate, methylene dichloride, phenol, methylene chloride, or n-methylpyrolldone. regulatory compliance the HFCT-5202 is intended to enable commercial system designers to develop equipment that complies with the various regulations governing certifica- tion of information technology equipment. see the regulatory compliance table 1 for details. additional information is available from your hewlett- packard sales representative. electrostatic discharge (esd) normal esd handling precautions for esd sensitive devices should be followed while using the HFCT-5202. these precautions include using grounded wrist straps, work benches, and floor mats in esd controlled areas.
6 additionally, static discharges to the exterior of the equipment chassis containing the transceiver parts must also be considered. if the duplex sc connector is exposed to the outside of the equipment chassis it may be subject to whatever esd system level test criteria that the equip- ment is intended to meet. figure 5. recommended board layout hole pattern. electromagnetic interference (emi) most equipment designs utilizing these high-speed transceivers from hewlett-packard will be required to meet the require- ments of fcc in the united states, cenelec en55022 (cispr 22) in europe, and vcci in japan. the HFCT-5202 has been characterized without a chassis enclosure to demonstrate the robustness of the parts integral shielding. performance of a system containing these transceivers within a well designed chassis is expected to be better than the results of these tests with no chassis enclosure. immunity equipment utilizing these hfct- 5202 transceivers will be subject to radio-frequency electromagnetic fields in some environments. these transceiv- ers, with their integral shields, have been characterized without the benefit of a normal equip- ment chassis enclosure and the results are reported below. performance of a system con- taining these transceivers within a well-designed chassis is expected to be better than the results of these tests without a chassis enclosure. d b e top view c a f dim. millimeters inches min. typ. max. min. typ. max. 1.8 0.7 20.32 33.02 2.54 2.54 2.0 0.9 0.071 0.027 0.8 1.3 0.1 0.1 0.079 0.035 a b c d e f
7 figure 6. package outline drawing and pinout. a area reserved for process plug b c h d g j s ? l (18 x) note 1 n p q note 1: solder posts and electrical pins are tin/lead plated. f ref. e m ref. k typ. 8 pls ? r (2 x) note 1 18 = v eer 17 = rd 16 = rd 15 = sd 14 = v ccr 13 = v cct 12 = td 11 = td+ 10 = v eet top view n/c n/c 1 = ref clk 2 = lck ref 3 = clk 4 = clk+ 5 = l mon (? 6 = l mon (+) 7 = t xdis 8 = n/c 9 = p mon rx tx dim. millimeters inches min. typ. max. min. typ. max. 12.70 0.75 3.30 12.70 20.32 52.02 25.40 11.1 10.35 0.500 0.030 0.130 0.500 0.800 2.048 1.000 0.437 0.407 a b c d e f g h j dim. millimeters inches min. typ. max. min. typ. max. 0.46 1.27 2.54 3.12 2.54 33.02 15.88 20.32 0.53 1.32 0.018 0.050 0.100 0.123 0.100 1.300 0.625 0.800 0.021 0.052 k ? l m n p q ? r s
8 table 1. regulatory complianceCtypical performance feature test method performance electrostatic discharge mil-std-883c class 1 (>1000 v) (esd to the electrical pins) method 3015.4 electrostatic discharge variation of products of this design typically withstand at least (esd) to the duplex sc iec 801-2 25 kv without damage when the duplex sc receptacle connector receptacle is contacted by a human body model probe. electromagnetic fcc class b typically provide 4 db margin to fcc class b interference (emi) cenelec en55022 and a 1 db margin to the other noted standard class b (cispr 22b) limits when tested at a certified test range with vcci class 2 the transceiver mounted to a circuit card without a chassis enclosure at frequencies up to 1 ghz. margins above 1 ghz are dependent on customer board and chassis designs. immunity variation of iec 801-3 typically show 1.3 db penalty from a 3 v/m field swept from 10 to 450 mhz applied to the transceiver when mounted to a circuit card without a chassis enclosure. eye safety iec 825/cdrh class 1 HFCT-5202 license pending. performance specifications absolute maximum ratings parameter symbol minimum maximum units storage temperature t s C40 +85 c operating temperature C HFCT-5202a/c C C40 +85 c operating temperature C HFCT-5202b/d C 0 +70 c lead soldering temperature/time C C +240/10 c/s output current (other outputs) i out 030ma input voltage C gnd v cc v power supply voltage C 0 +6 v
9 operating environment parameter symbol minimum maximum units power supply voltage ecl operation v cc -4.95 -5.45 v power supply voltage pecl operation v cc +4.75 +5.25 v ambient operating temperature C HFCT-5202a/c t op C40 +85 c ambient operating temperature C HFCT-5202b/d t op 0 +70 c transmitter section (ambient operating temperature, v cc = 4.75 v to 5.25 v) parameter symbol minimum maximum units notes output center wavelength l ce 1261 1360 nm C output spectral width (rms) dl C 7.7 nm C average optical output power p o C15 C8.0 dbm 1 extinction ratio e r 8.2 C db C power supply current i cc C 140 ma 2 output eye compliant with bellcore tr-nwt-000253 and itu recommendation receiver section (ambient operating temperature, v cc = 4.75 v to 5.25 v) parameter symbol minimum typical maximum units notes receiver sensitivity C C28 C C dbm 3 maximum input power C C7.0 C C dbm C alarm on C C42 C C31 dbm C hysteresis C 0.5 C 4.0 db C power supply current i cc C 180 290 ma 4 data outputs ecl/pecl alarm output ecl/pecl clock outputs ecl/pecl jitter tolerance itu g.958 compliant notes: 1. output power is power coupled into a single mode fiber. 2. the power supply current varies with temperature. maximum current is specified at v cc = maximum at maximum temperature (not including terminations) and end of life. 3. minimum sensitivity and saturation levels for a 2 23 C1 prbs with 72 ones and 72 zeros inserted. (itu recommendation g.958). 4. the current excludes the output load current.
10 table 2. pin out table pin symbol functional description mounting the mounting studs are provided for transceiver mechanical attachment to the circuit studs board. they are embedded in the nonconductive plastic housing and are not connected to the transceiver internal circuit. they should be soldered into plated-through holes on the printed circuit board. 1 ref clk reference clock - optional feature reference clock can be used as an optional, internally generated local receiver clock when the input optical signal is disrupted. see pin 2 lck ref- description. this input is not required for the normal operation of the clock recovery circuit. this is a single- ended pecl input. if this reference clock input is used, provide a 19.44 mhz external reference clock signal and terminate at this input pin with standard pecl techniques. if this reference clock input is not used, leave the input open-circuited. with the input open-circuited, an internal pull-down resistor will bias this input to a low-state condition. 2 lck refC lock-to-reference clock bar - optional feature lock-to-reference clock bar can be used to help manage the performance of the receiver when the input optical signal is disrupted. when used, it places the received data outputs in static states and it triggers an internally generated local receiver clock to be output on clk/clk- in substitution of recovered clock. this is a single-ended pecl input. for normal operation of the transceiver, connect this lock-to-reference-bar input to v cc or a pecl high-state (v ih ) which causes the internal cdr circuit to output recovered differential clock on clk/clk- and re-timed differential data on rd/rd-. for optional use to make static the received data outputs and to output the internally generated local receiver clock, connect lck ref- input to a pecl low-state (v il ), or leave this input open-circuited. when this is done it will cause: 1) the received data outputs to change to static pecl logic levels (rd = v ol and rd- = v oh ), 2) the internal cdr circuit to switch over to using the external reference clock, if provided, as the timing source to generate a 155.52 mb/s clock output on clk/clk-. if the feature is used, one way to implement it is to connect this pin to signal detect directly with a single pull-down resistor of 10 k w to ground. if this lock-to-reference feature is not used, this pin must be connected directly to v cc or a pecl high-state to disable it. 3 clkC received recovered clock out bar see pins 1 & 2 for optional, local generated clock output. the rising edge occurs coincident with the edges of the received data output. the falling edge occurs in the middle of the received data baud period. terminate this high-speed, differential clock output with standard pecl techniques at the clock input point of the follow-on device.
11 table 2. pin out table (continued) pin symbol functional description 4 clk+ received recovered clock out see pins 1 and 2 for optional, local generated clock output. the falling edge occurs coincident with the edges of the received data output. the rising edge occurs in the middle of the received data baud period. terminate this high-speed, differential clock output with standard pecl techniques at the clock input point of the follow-on device. 5l mon (C) laser bias monitor (-) this analog current is monitored by measuring the voltage drop across a 10 ohm resistor placed between high impedance resistors connected to pins 5 and 6 internal to the transceiver. 6l mon (+) laser bias monitor (+) this analog current is monitored by measuring the voltage drop across a 10 ohm resistor placed between high impedance resistors connected to pins 5 and 6 internal to the transceiver. 7 txdis transmitter disable transmitter output disabled: v cct C 1.5 v v 7 v cct . transmitter output uncertain: v cct C 4.2 v v 7 v cct C 1.5 v. transmitter output enabled: v eet v 7 v cct C 4.2 v or open circuit. 8 n/c 9p mon power monitor the analog voltage measured at this high impedance output provides an indication of whether the optical power output of the laser diode is operating within the normal specified power output range per the following relationships: high light indication: v 9 v eet + 1.7 v. normal operation: v 9 @ v eet + 1.2 v. low light indication: v 9 v eet + 0.7 v. 10 v eet transmitter signal ground directly connect this pin to the transmitter signal ground plane. 11 td+ transmitter data in terminate this high-speed, differential transmitter data input with standard pecl techniques at the transmitter input pin. 12 tdC transmitter data in bar terminate this high-speed, differential transmitter data input with standard pecl techniques at the transmitter input pin. 13 v cct transmitter power supply provide +5 v dc via the recommended transmitter power supply filter circuit. locate the power supply filter circuit as close as possible to the v cct pin. 14 v ccr receiver power supply provide +5 v dc via the recommended receiver power supply filter circuit. locate the power supply filter circuit as close as possible to the v ccr pin.
for technical assistance or the location of your nearest hewlett-packard sales office, distributor or representative call: americas/canada: 1-800-235-0312 or 408-654-8675 far east/australasia: call your local hp sales office. japan: (81 3) 3335-8152 europe: call your local hp sales office. data subject to change. copyright ? 1997 hewlett-packard co. obsolete: 5965-8277e printed in u.s.a. 5966-1882e (11/97) table 2. pin out table (continued) pin symbol functional description 15 sd signal detect normal input optical levels to the receiver result in a logic 1 output. low input optical levels to the receiver result in a fault indication shown by a logic 0 output. signal detect is a single-ended, low-power, pecl output. since sd is a low-power pecl output, complete the interconnection of sd output with other pecl inputs using a 10 k w pull-down resistor to v ee to allow biasing of the interconnection. do not load this sd output with standard pecl, 50 w to v cc C 2 v, termination. if signal detect output is not used, leave it open-circuited. this signal detect output can be used to drive a pecl input on an upstream circuit, such as, signal detect input, loss of signal-bar input, or to optionally drive the lock-to-reference-bar input (pin 2) of this transceiver. 16 rdC retimed receiver data out bar terminate this high-speed, differential, pecl output with standard pecl techniques at the follow-on device input pin. 17 rd+ retimed receiver data out terminate this high-speed, differential, pecl output with standard pecl techniques at the follow-on device input pin. 18 v eer receiver signal ground directly connect this pin to receiver signal ground plane. ordering information HFCT-5202 x a = C40 to +85 c black b = 0 to +70 c black c = C40 to +85 c blue d = 0 to +70 c blue recommended part numbers: HFCT-5202c HFCT-5202d class i laser product: this product conforms to the applicable requirements of 21 cfr 1040 at the date of manufacture. date of manufacture: ___________________ hewlett-packard ltd., whitehouse rd., ipswich, england www.hp.com/go/fiber

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